This application relies for priority upon Korean Patent Application No. 2001-1102, filed on Jan. 9, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a NAND type flash memory device, and more particularly to a NAND type flash memory device having dummy region.
A flash memory device is a kind of nonvolatile memory device in which data bits are concurrently erased from all of the memory cells or one of the memory cell blocks. Flash memory devices are generally classified into NOR and NAND types according to the composition. The NAND type memory device is formed to have one string as a unit. In one string, 8, 16, or 32 memory cell transistors are formed one after another. Also, in each string, a bit line contact is formed at a drain region of a string select line and a common source line is in contact with a source region of a ground select line. Thus, there are no contacts between the memory cell transistors adjacent along an active region in one string. This is advantageous to increase the integration density of the memory device compared with a dynamic random access memory (DRAM) device.
Owing to line resistance, gate lines including the string select line, the ground select line, and the common source line in the flash memory device are not continuously formed over the whole chip, but are divided into several blocks, each of which is designed to be supplied with same voltage. Also, to increase conductivity, the string select line or the ground select line does not have a double gate structure having a floating gate and a control gate, but has a dummy gate line formed of a control gate layer and a lower gate line connected at given intervals with the dummy gate line through contacts. By reason of the same, line shaped portions of an isolation layer and line shaped sub-regions of an active region defined by means of the isolation layer do not have the same width in all areas, but have different widths in some areas.
FIG. 1 is a top plan view showing a potion of a cell area of a conventional NAND type flash memory device. As shown in FIG. 1, the cell area of the flash memory device includes a NAND cell unit in which a string select gate line SSL, plural word lines WL1-WLN, and a ground select gate line GSL are arranged in order in a longitudinal direction of an active region. The active region overlapped with bit lines BL is defined to repeatedly dispose strings in a longitudinal direction of the word lines by means of an isolation layer. The isolation layer STI has plural narrow portions STIs and a wide portion STIL. On the wide portion STIL of the isolation layer STI, butted contacts BC are formed.
In forming of the cell area of the flash memory device shown in FIG. 1, an isolation layer is first formed on a substrate to form an active region by using a shallow trench isolation (STI) process. The active region comprises a plurality of line shaped sub-regions which are defined respectively by a plurality of elongated openings or gaps of an isolation layer STI. In the STI process, photo-exposure process for forming trenches on the substrate is carried out. After the trenches are filled with the isolation layer, a pattern is obtained in which the line shaped sub-regions of the active region and plural narrow portions STIs and a wide portion STIL of the isolation layer are repeatedly arranged. However, under the influence of the wide portion STIL of the isolation layer, the line shaped sub-regions of the active region and the narrow portions STIs adjacent to the wide portion STIL of the isolation layer become had widths different from those remote therefrom. This variation may result in a decrease of the process margin as well as difficulty in device design, thereby decreasing the quality of the device.
Also, in case a chemical mechanical polishing (CMP) process is carried out in forming of the isolation layer, the wide portion STIL of the isolation layer is dented at the center thereof owing to a dishing phenomenon. The dented portion results in a problem such as forming step coverage in a subsequent process.
To solve these problems, in case there is any region or portion having wide width between the line shaped sub-regions of the active region or plural narrow portions of the isolation layer, a dummy region can be formed therebetween or in the middle thereof. FIG. 2 is a top plan view showing a portion of the NAND cell unit of the cell area of the conventional flash memory device in which a dummy region is formed.
Referring to FIG. 2, three line shaped sub-regions DA1 to DA3 of an active region adjacent to a wide portion STIL of an isolation layer and two narrow portion STIs of the isolation layer therebetween form a dummy region. In order to increase the integration density of the flash memory device, it is preferable that the isolation layer is formed by using a STI process. In the STI process, the isolation layer is formed by means of a chemical vapor deposition (CVD). However, in case the integration density of the flash memory device is increased, widths of the line shaped sub-regions or portions of the active region and the isolation layer have to be decreased, thereby to increase a ratio of length to width of trenches to be filled with the isolation layer. In this case, voids are apt to be formed in the isolation layer. In FIG. 2, it is shown that voids are generated in the narrow portions STIs of the isolation layer between the lined shaped sub-regions DA1 to DA3 of the active region forming the dummy region. After forming of isolation layer, a cleaning process removes an upper portion of the isolation layer in which the voids are formed, exposing the voids. The voids are filled with a silicon during forming of the silicon floating gate layer. However, when the silicon floating gate layer is etched to form the floating gate intermediate pattern, silicon in the voids is not etched well, so that a kind of wiring pattern 3 parallel to the active region is formed. At this time, what the wiring pattern 3 is connected with cell transistors corresponding to the word lines in the line shaped sub-regions of the active region forming the dummy region is worth little consideration since they will become dummy transistors. However, in case the wiring pattern 3 formed in the voids is crossed with the floating gate layer of the ground select line GSL and the active region in which the common source line CSL is to be formed, a short circuit between the ground select line GSL and the common source line CSL may be occurred. In FIG. 3 and FIG. 4, there is clearly illustrated that the wiring pattern 3 formed in the voids of the line shaped sub-regions STIs of the isolation layer is electrically connected with the ground select line GSL and the common source line CSL. Thus, the dummy region formed to prevent an abrupt change in width of given portions of the isolation layer from having influence on width of adjacent portions thereof during the optical lithography may result in another problem such as the short circuit between the ground select line GSL and the common source line CSL.
It is an object of the present invention to provide an improved NAND type flash memory device that is free of defects formed in the dummy region.
It is another object of the present invention to provide an improved NAND type flash memory device, which is free short circuit between a common source line and a ground select line due to voids formed in an isolation layer in a dummy region.
These and other objects are provided, according to the present invention, by a NAND type flash memory device having a dummy region forming a dummy pattern in which a common source line is formed to cross only with an isolation layer adjacent an active region of a normal pattern forming memory cells.
The NAND type flash memory device of the present invention includes an isolation layer having a plurality of line shaped portions formed parallel to each other on a substrate; an active region having a plurality of line shaped sub-regions defined by means of the isolation layer, each line shaped sub-region having a plurality of channel regions and a plurality of source/drain regions alternate with each other on the substrate in a cell area; a common source line connected electrically with at least one of the source/drain regions and one portion of the line shaped sub-regions of the active region, and crossing at least the one portion of the line shaped sub-regions of the active region; and a group of gate lines formed to cross the line shaped sub-regions of the active region, including ground select lines, a plurality of word lines, and string select lines arranged in order in a longitudinal direction of the line shaped sub-regions of the active region from the common source line, to form gate electrodes insulated from the channel regions by a gate insulating layer, in each of the channel regions on junction regions which crossed with the line shaped sub-regions of the active region. The other portion of the line shaped sub-regions of the active region is composed of a dummy region forming a dummy pattern, and the common source line is formed to cross only line shaped portions of the isolation layers which are in contact with the one portion of the line shaped sub-regions of the active region forming a normal pattern except the dummy pattern.
The flash memory device of the present invention further includes a plurality of bit lines connected through contacts with the one portion of the line shaped sub-regions of the active region forming the normal pattern on the opposite side of sides of the string select lines adjacent to the word lines, and arranged parallel to the one portion of the line shaped subregions of the active region. On the other portion of the line shaped sub-regions of the active region forming the dummy region there are no bit lines. However, united source wiring instead of the bit lines can be formed on one line shaped sub-region of the active region forming the dummy pattern adjacent to the normal pattern. The common source line is extended to the one line shaped sub-region of the active region adjacent to the normal pattern. A contact hole for the united source wiring is formed in the additional insulating layer at a region in which the common source line is crossed with the one line shaped sub-region of the active region forming the dummy pattern to be filled when the conductive layer for forming the bit lines is deposited, so that a contact connecting the common source line with the united source wiring is formed.
The line shaped sub-regions of the active region are divided into a plurality of blocks, and the dummy region is formed at both sides of the blocks. Also, the blocks are divided on the basis of the line shaped portions of the isolation layer having wide widths on which butted contacts are formed.
In the flash memory device of the present invention, the number of the word lines is one selected from 8, 16, and 32. Also, the common source line is formed of a wall shape having a lower end which is in contact with the one portion of the line shaped sub-regions of the active region and the line shaped portions of the isolation layer between or adjacent to the one portion of the line shaped sub-regions of the active region at a region in which the common source line is formed. The isolation layer can be formed by using CVD process through STI process. The ground select lines are formed by patterning the same polysilicon layer as that of floating gates of the word line.
In the flash memory device of the present invention, width of the line shaped portions or sub-regions of the isolation layer or the active region of the dummy pattern adjacent to the normal pattern is narrower than that of the dummy pattern remote from the normal pattern to be almost the same as that of the normal pattern.